Semiconductor Scaling

The "7-nanometer node" is a lie. Not in the sense that it's approximately wrong — in the sense that it has no physical referent whatsoever. The most critical features of a 7nm transistor are considerably larger than 7 nanometers, and this disconnect between nomenclature and reality has been the case for about two decades. The node number is a marketing artifact, a ghost of a measurement system that stopped tracking actual dimensions sometime in the 1990s.¹

How We Got Here

Once upon a time, the node number meant something. From the Intel 4004 in 1971 through the mid-1990s, two physical dimensions — metal half-pitch (half the distance between adjacent metal interconnect lines) and gate length (the space between source and drain) — were roughly equal, and both tracked the node number. Each generation shrank both dimensions by about 30%, which halved the transistor area and doubled the density. Moore's Law wasn't a law of physics — it was an observation about the rate at which engineers could make two numbers smaller.

The uncoupling began in the mid-1990s, when chipmakers started shrinking gate length more aggressively than other features to keep squeezing out performance gains. By the 130nm node, transistors had 70nm gates. The node name still followed the old naming cadence, but it no longer corresponded to any dimension you could find on the actual silicon. When Intel switched to FinFETs at the "22nm" node in 2011, the devices had 26nm gate lengths, a 40nm half-pitch, and 8nm-wide fins. As Paolo Gargini — IEEE Life Fellow and Intel veteran — puts it, the node number "had by then absolutely no meaning, because it had nothing to do with any dimension that you can find on the die."¹

The practical consequence isn't just semantic confusion. It's that the node system makes semiconductor technology look like it's approaching a wall — a countdown to some physical limit where 1nm is scarcely five silicon atoms wide. This discourages students from entering the field and obscures the real avenues for continued progress.

GMT: Going Back to Dimensions

Gargini's proposal, developed through the IEEE International Roadmap for Devices and Systems, is to replace the single node number with three physically meaningful values: contacted Gate pitch (G), Metal pitch (M), and the number of Tiers of devices (T).

Contacted gate pitch is the minimum distance from one transistor's gate to another's. Metal pitch is the minimum distance between horizontal interconnects. These two values are the "least common denominator" for creating logic — their product gives a good estimate of the minimum possible transistor area. The "5nm" chips shipping in 2020 would be described as G48M36T1: 48nm gate pitch, 36nm metal pitch, one tier. It doesn't roll off the tongue, but it tells you something real.¹

The T term is the key to why this metric doesn't have a doomsday clock feel. Around 2029, metal pitch will approach the limits of extreme ultraviolet lithography. After that, the way forward is monolithic 3D — stacking layers of transistors on top of each other. Belgian research firm Imec, France's CEA-Leti, and Intel are all developing approaches where NMOS and PMOS transistors are built one atop the other. Carbon nanotube transistors, processable at lower temperatures, might get there even sooner. The T value starts at 1 and goes up.

LMC: A System-Level View

A group of prominent academics from Berkeley and Stanford — including the three engineers credited with inventing the FinFET — took a different approach. Their concern wasn't just measurement accuracy; it was framing. They wanted a metric with no natural endpoint, where numbers go up with progress rather than down, and that captures more than just transistor geometry.

Their LMC metric describes three densities: Logic (DL, in transistors per square millimeter), Memory (DM, in cells per square millimeter), and Connectivity (DC, in interconnects per square millimeter between logic and memory). A system combining the best published values as of 2020 would be described as [260M, 200M, 12K].¹

The insight behind LMC is that a computer is fundamentally logic, memory, and the connections between them. Improvements in any one dimension without the others create bottlenecks. Historical data shows that balanced increases across all three have been going on for decades — an implicit architectural constraint that holds from mobile processors up to supercomputers. The metric captures this balance explicitly.

The memory dimension (DM) is currently dominated by DRAM, but alternative technologies — magnetoresistive RAM, ferroelectric RAM, phase-change RAM — are in production. The connectivity dimension (DC) has historically improved in discrete jumps as packaging technology advances, from single-die SoCs to chiplet architectures to 3D chip stacking. Cerebras's approach of embedding all memory on a single massive silicon slab represents one extreme of the DC question.

Does Anyone Care?

The honest answer: industry consensus doesn't exist yet. Intel's CTO agreed that "picking something that is agreed upon, even if imperfect, is more useful than the current node branding." AMD uses something similar to LMC internally. But GlobalFoundries — which stopped pursuing leading-edge nodes in 2018 — argues that scaling metrics are "useful really only in applications dominated by scaling," and most of the semiconductor industry isn't in that race.

There's also the critique that neither metric captures what customers actually want: the tradeoff between area density, performance, power, and cost. No single number can, and maybe that's fine. The point isn't to compress all of semiconductor progress into one figure — it's to stop using a number that actively misleads.

What matters for the longer term is the talent pipeline. If the dominant narrative says transistors stop shrinking in ten years, ambitious students go elsewhere. If the narrative is that scaling continues through 3D integration, new materials, and architectural innovation — which it does — then the field remains worth entering. The GMT and LMC proposals are as much about storytelling as measurement. The old story says the road ends. The new story says the road turns.